DUBLIN, Dec 1, 2016 /PRNewswire/ --
Research and Markets has announced the addition of the "TSMC Integrated Fan-Out (inFO) Package Apple A10 iPhone 7 Plus Application Processor: Analysis" report to their offering.
Each year, Apple integrates new technology and innovation inside the iPhone. This year with the iPhone 7, Apple is the first to bring Package on Package (PoP) Wafer-Level Packaging (WLP) at the consumer scale. For its new application processor packaging, the A10, Apple has considered to use TSMC's new inFO-PoP (integrated Fan-Out PoP) technology.
Located under the DRAM package on the main board, the application processor (AP) is packaged using PoP. Depending on the version (iPhone 7 or iPhone 7 Plus), the DRAM memory has different space management.
The Apple A10 is a wafer-level package using TSMC's packaging technology with copper pillar as Through inFO Via (TIV) to replace the well-known Through Molded Via (TMV) technology. With this new technology, Apple marked a huge breaking point with the old traditional PoP found in the previous generations of his APs. In this report, we will show the differences and the innovations of this package: Copper Pillars, Redistribution layer, patent identification, silicon high density capacitor integration, The detailed comparison with the Exynos 8 and the Snapdragon 820 will give the pro and the cons of the inFO technology compared to PoP packaging used in the market.
Thanks to this inFO process, Apple is able to propose a very thin package on package, with a high number of I/O pads and better thermal management. The result is a very cost-effective component that can compete with any well-known PoP. In the report, the cost comparison is also including in order to highlight the difference.
This report also includes a technical comparison with previous Apple AP, the A9.
Key Topics Covered:
1. Overview / Introduction
2. Company Profile and Supply Chain
3. Physical Analysis
- Physical Analysis Methodology
- iPhone 7 Plus disassembly
- A10 Packaging Analysis
- Land-Side Decoupling capacitor
- PoP Comparison (Samsung's PoP and Shinko's MCeP)
- A10 Die Analysis
- Comparison with previous generation (A9)
4. Manufacturing Process Flow
- Chip Fabrication Unit
- Packaging Fabrication Unit
- inFO Package Process Flow
5. Cost Analysis
- Synthesis of the cost analysis
- Supply Chain Description
- Yield Hypotheses
- A10 Die Cost Analysis
- inFO Package Cost Analysis
- Final Test Cost
- Component Cost
6. Estimated Price Analysis
7. Cost & price comparison with Samsung's PoP & Shinko's MCeP
For more information about this report visit http://www.researchandmarkets.com/research/nmb7st/tsmc_integrated
Laura Wood, Senior Manager
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SOURCE Research and Markets