The Number of Packages Utilizing WLP Will Equal Flip Chip Shipments in 2018 And Then Continue Growing at a CAGR of 15%
Flip Chip/WLP Manufacturing and Market Analysis, the number of packages utilizing WLP will equal Flip Chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for Flip Chip, as shown in the graphic below.
Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT. Flip chip technology is slowly replacing wire bonding for many high-performance chips. Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA).
This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.
Fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. The FO-WLP process typically starts when individual dies are placed on double-sided tape sitting on a silicon carrier. The die is covered with a mold compound, and the carrier and tape are removed, leaving the die embedded in the mold. The wafer is turned over; an RDL is created, and solder balls are formed on top, just as in a Fan-in WLP. The extra panel surface area around the chip permits I/Os to be both fanned in over the chip and fanned out across the mold compound, making it possible to accommodate a larger number of I/Os.
One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor. The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.
Chapter 4 Lithography Issues And Trends 4.1 Issues 4.1.1 Technical Performance 4.1.2 Capital Investment 4.1.3 Cost Of Consumables 4.1.4 Throughput 4.1.5 Ease Of Use 4.1.6 Flexibility 4.1.7 Equipment Support 4.1.8 Resolution 4.1.9 Solder Bumping Capabilities 4.1.10 Gold Bumping Capabilities 4.2 Exposure Systems 4.2.1 Introduction 126.96.36.199 Reduction Steppers 188.8.131.52 Full-Field Projection 184.108.40.206 Mask Aligners 220.127.116.11 1X Steppers 18.104.22.168 2X Steppers 4.3 Competitive Technologies 4.3.1 Inkjet Printing 4.3.2 Stencil/Screen Printing 4.3.3 Electroless Metal Deposition
Chapter 5 UBM Etch Issues And Trends 5.1 Introduction 5.2 Technology Issues And Trends 5.2.1 Process Flow 5.2.2 Etch Process 5.2.3 Etch Chemistry 5.3 Batch Versus Single-Wafer Etching
Chapter 6 Metallization Issues and Trends 6.1 Introduction 6.2 Sputtering Metallization 6.2.1 Gold Bump 6.2.2 Solder Bumping 22.214.171.124 T I / Cu and TiW / Cu 126.96.36.199 Al / NiV / Cu 188.8.131.52 T i / N i (V) and TiW / Ni ( V ) 184.108.40.206 Cr / Cr-Cu / Cu 6.2.3 Copper Bumping 6.3 Electrodeposition