Through-Silicon Via (TSV) is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction.
TSV provides the high-bandwidth interconnection between stacked chips. The different TSV processes, which are more complex than initially anticipated, are analyzed.
This report analyzes the market for TSV ICs by units and wafers, and for equipment and materials used in their manufacture.
Key Topics Covered:
Chapter 1 Introduction
Chapter 2 Insight Into Critical Issues
Driving Forces In 3-D TSV
Benefits of 3-D ICs With TSVs
Requirements For A Cost Effective 3-D Die Stacking Technology
TSV Technology Challenges
TSV Supply Chain Challenge
Limitations of 3-D Packaging Technology
Chapter 3 Cost Structure
Cost Structure of 3-D chip Stacks
Cost of Ownership
Chapter 4 Critical Processing Technologies
Plasma Etch Technology
Thin Wafer Bonding
Chapter 5 Evaluation Of Critical Development Segments