DUBLIN, Feb 16, 2017 /PRNewswire/ --

Research and Markets has announced the addition of the "TSMC DTC: Reverse Costing Analysis" report to their offering.

Thanks to TSMC, Integrated Passive Devices (IPD) are back in mobile industry. Information about the Apple A10 integrated in the latest flagship of the firm, the iPhone 7, mentioned the use of the first PoP Wafer Level Packaging for consumer developed by TSMC named inFO-PoP (integrated Fan-Out - Package-on-Package). But for this occasion, TSMC also integrated a brand new technology that was never proposed for high volume product. For the A10 application processor, TSMC integrated High density deep trench capacitor (DTC) on silicon substrate as Land-Side decoupling capacitor.

Located under the inFO PoP, the Land-Side Capacitor (LSC) is in flip chip configuration and supported by an extra layer on the PCB.

The LSC is a high density deep trench capacitor on silicon substrate developed by TSMC using trench capacitor to increase the capacitive area without changing the footprint of the component. Compared to MLCC technology, TSMC marked a huge breaking point with a component that can compete with ceramic capacitor.  In this report, we show the differences and the innovations of this capacitor: trench silicon, oxide deposition, The detailed comparison with the LSC in the Exynos 8 and the Snapdragon 820 will give the pro and the cons of the TSMC's LSC technology.

Thanks to this DTC process, TSMC is able to propose a very thin capacitor, with a high density and same footprint as MLCC 0204. The result is a very cost-effective component that can compete with any ceramic capacitor. In the report, the cost comparison is also including in order to highlight the difference with ceramic capacitor.

Key Topics Covered:

Overview / Introduction

Company Profile and Supply Chain

Physical Analysis

- Physical Analysis Methodology

- iPhone 7 Plus disassembly

- A10 & LSC Die removal

- LSC Packaging Analysis

- Package View and Dimensions

- Package Cross-Section

- Capacitor Die Analysis

- Die View and Dimensions

- Die marking

- Die Overview and Delayering

- Die Cross-Section

- Die process

- Land-Side Decoupling Capacitor Comparison

- Packages LSC comparison

- Cost & Performances comparison

Manufacturing Process Flow

- Chip Fabrication Unit

- DTC Process Flow

Cost Analysis

- Synthesis of the cost analysis

- Supply Chain Description

- Yield Hypotheses

- Die Cost Analysis

- Wafer Cost

- Die Cost

- Final Test Cost

- Component Cost

Estimated Price Analysis

For more information about this report visit http://www.researchandmarkets.com/research/x2gd27/tsmc_dtc_reverse

Media Contact:

Research and Markets

Laura Wood, Senior Manager

press@researchandmarkets.com

For E.S.T Office Hours Call +1-917-300-0470

For U.S./CAN Toll Free Call +1-800-526-8630

For GMT Office Hours Call +353-1-416-8900

U.S. Fax: 646-607-1907

Fax (outside U.S.): +353-1-481-1716

Related Links

http://www.researchandmarkets.com

SOURCE Research and Markets